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Neural Network Based Design Optimization of 14 nm Node Fully Depleted SOI FET for SoC and 3DIC Applications

Hyeok Yun and Jun Sik Yoon and Jinsu Jeong and Seunghwan Lee and Hyun Chul Choi and Rock Hyun Baek

DOI
10.17023/f7f1-hp79
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    Length: 01:05:39

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