Switching Noise Reduction of Synchronous DC-DC Buck Converter based on Smart Power Stages by Minimizing Parasitic Inductances

This paper introduces the smart power stage (SPS) chip for synchronous buck converter which has the feature of minimized parasitic inductances. Through analyzing the drain-source voltage of switching MOSFETs based on the parasitic inductances in one switching interval, the switching noise is obtained. Compared with the buck converter using discrete switching components, SPS built buck converters have greatly improved the voltage stress, eliminating false triggering pulses and increasing efficiency. Simulation results and experimental platforms of SPS-buck and DSC-buck were established to verify the correctness of the theory.