Achieving a Sub Miliohm Load Line on a Discrete Graphics Product

The Direct Current Load Line (DCLL) and the Alternating Current Load Line 3 (ACLL3) target of 0.5mOhm has been defined for a graphics core power delivery network in order to achieve the preferred peak performance on the next generation discrete graphics product. The pathfinding effort led to explore various innovative solutions to have a line of sight for achieving this challenging impedance target, which includes A. Study of various stack up and routing strategies to achieve the lower Resistance path (Rpath) B. Novel idea of bulk capacitors provision beneath System on Chip (SoC) cavity to lower Load Line (LL) around the Voltage Regulator Module (VRM) bandwidth C. Improved Power Integrity (PI) design methodology for an accurate ACLL and reasonable DCLL estimation D. Enhancement in Package Design for Manufacturing (DFM) rules to gain extra margins