Exploration Methodology For Bti-Induced Failures On Rram-Based Edge Ai Systems
Alexandre Levisse, Marco Rios, David Atienza, Miguel Peon
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While resistive switching memory technologies (RRAM) are seen by most of the scientific community as an enabler for Edge-level applications such as embedded deep Learning, AI or signal processing of audio and video signals, going beyond a ``simple'' replacement of eFlash in micro-controller and introducing RRAM inside the memory hierarchy is not as straightforward as it could be perceived. Indeed, integrating a RRAM technology (inside the cache hierarchy for e.g.) requires higher endurance requirement than for eFlash replacement, and thus necessitates relaxed programming conditions. By doing so, the reliability bottleneck is moved from programming to the read operations (i.e., read margin is reduced and the risk of read failure is increased). Based on this observation, in this work, we propose to explore how Edge-level applications running on a RRAM-based Edge device could fail because of Bias Temperature Instability (BTI). BTI causes threshold voltage (Vt) degradation on the transistors along the memory WordLines (WL), leading to a reduction of the read margin along regularly used WLs. Our simulations highlight the fact that transistor-level reliability can be critical for embedded RRAM and that specific workload aware simulation frameworks are required to assess their effects.