Directions, Challenges and Opportunities in Heterogeneous Integration

Abstract: Heterogeneous Integration (HI) is a powerful and crucial enabler for the continued growth of computing and communication performance. Advanced packaging technologies are critical enablers of HI because of their importance as compact, power efficient platforms. This talk will focus on the tremendous opportunities in different application environments and focus on the projected evolution of advanced packaging architectures. Interest in HI research has picked up in recent years and this opens up greater collaboration opportunities between academia and industry. Specific examples, showing how product implementations take advantage of currently available HI technologies, to provide an unprecedented level of performance, will be used to describe the challenges and opportunities in developing robust, next generation advanced package architectures. A broad scope roadmap of the future generated as part of an industry-academic collaboration will be discussed in this context to highlight the opportunities generated by HI. Intel’s engagement with federal programs in developing State-of-the-Art packaging solutions using Advanced Packaging technologies will also be described. Biography: Ravi Mahajan is an Intel Fellow responsible for Assembly and Packaging Technology Pathfinding for future silicon nodes. Ravi also represents Intel in academia through research advisory boards, conference leadership and participation in various student initiatives. He has led Pathfinding efforts to define Package Architectures, Technologies and Assembly Processes for multiple Intel silicon nodes including 90nm, 65nm, 45nm, 32nm, 22nm and 7nm silicon. Ravi joined Intel in 1992 after earning his Ph.D. in Mechanical Engineering from Lehigh University. He holds the original patents for silicon bridges that became the foundation for Intel’s EMIB technology. His early insights have led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques for thermo-mechanical stress model validation. His contributions during his Intel career have earned him numerous industry honors, including the SRC’s 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI Award from SEMITHERM, the 2016 Allan Kraus Thermal Management Medal & the 2018 InterPACK Achievement award from ASME, the 2019 “Outstanding Service and Leadership to the IEEE” Awards from IEEE Phoenix Section & Region 6 and most recently the 2020 Richard Chu ITherm Award and the 2020 ASME EPPD Excellence in Mechanics Award. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT. He has long been associated with ASME’s InterPACK conference and was Conference Co-Chair of the 2017 Conference. Ravi is a Fellow of two leading societies, ASME and IEEE. He was elected to the National Academy of Engineering in 2022 for contributions to advanced microelectronics packaging architectures and their thermal management.