Verilog and Spice Implementation of Genetic Algorithms

The research focuses on the implementation of Genetic Algorithms (GAs) in solving efficiency concerns with different types of circuits. Part of this project focuses on Ternary Content Addressable Memory (TCAM) circuits and how to maximize power and area efficiency of these circuits, while the other part focuses on improving cache timing efficiency. The TCAM circuit was described in HSPICE and its area and energy parameters were explored by a python script containing the GA. TCAM circuits with defined area and energy constrained in literature are compared with the results of GA-defined constraints to measure the performance of the GA. Our GA for cache optimization was implemented in C and utilized an LRU stack data structure and algorithm to evict physical memory frames. With a given memory trace, the implementation allowed us to view relationships between cache parameters and the effects they have on the miss rates and writebacks of a cache. The parameters outputted by the GA are then implemented in Verilog before the timing of the cache implementation is tested. Therefore, by using GA's, more efficient cache implementations that will minimize miss rate and other forms of cache inefficiency can be enacted, and as a result GA's can eventually be used to optimize more complex cache implementations.