PLL Architectures, Tradeoffs, and Key Application Considerations Slides and Transcript

A phase-locked loop (PLL) is a key building block in both wireless and wireline communications. For wireless systems, the DS PLL-based synthesizer plays a critical role in modern transceivers not only as a local oscillator but also as a phase modulator with direct digital modulation. As to wireline systems, low-jitter clock generation and versatile clock-and-data recovery circuits are critical in high data-rate I/O links. However, diversified PLL architectures with different tradeoffs make it difficult for circuit designers to choose the right design solution for various applications. This presentation discusses PLL architectures and application aspects with key design tradeoffs.