Clocking, clock distribution, and clock management in wireline and wireless subsystems Slides and Transcript

The performance of high-speed wireline and wireless subsystems highly depends on their clock quality. As data rates continue to scale aggressively, practical understanding of clocking design tradeoffs to optimize system power and area while achieving target bandwidth is crucial. In this short course, different aspects of clocking from circuit implementation to system architecture are discussed to provide insight into challenges and design choices for an optimum clocking solution. Clock generation techniques such as phase-locked loops (PLLs), delay-locked loops (DLLs) and injection-locked oscillators (ILOs) are also discussed. The design tradeoffs among various clock distribution techniques are presented. Clock recovery architectures and their impact on overall system performance are explained. To mitigate process variation, variation-tolerant circuits and clock calibration techniques are required. Energy-efficient clocking solutions can be achieved by active power minimization, amortization and aggressive power management methods. Examples of state-of-the-art clocking circuit and architecture solutions are presented.