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  • SSCS
    Members: Free
    IEEE Members: $10.00
    Non-members: $20.00
    Pages/Slides: 226
15 Feb 2022

Ten years ago or so, the term high-speed data converter was synonymous with sample rates on the order of a few hundreds of MHz, barring rare exceptions. Today, medium resolution ADCs (10-to-12b) and DACs clocked at tens of GHz, and even faster 6-to-8b converters, have been demonstrated without melting the die. So how could this level of advancement happen in the face of the end of Dennard scaling? The answer lies with the combination of architecture innovation and digital assistance. This presentation will give an overview of this rapidly (no pun intended) developing topic, aiming to illustrate the key design principles, their practical applicability, and will complement this material with examples of recently published multi-GSPS data converters.

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