Low-Jitter PLLs for Wireless Transceivers Slides and Transcript

Abstract- PLLs and frequency synthesizers are key building blocks in wireless transceivers. With the trend of higher data-rate, higher carrier frequency and higher order of modulation, the jitter or phase noise requirement becomes more demanding given a limited power budget. This tutorial starts from the fundamentals of PLL jitter and power consumption. Various sources of PLL jitter and power will be identified and analyzed, and design methodologies to optimize them on both the block and system level will be presented. Finally, the working principle and recent advances of the low jitter sub-sampling PLL architecture will be discussed.
Bio- Xiang Gao received the B.E. degree from the Zhejiang University, Hangzhou, China, in 2004 and the M.Sc. (cum laude) and Ph.D. (cum laude) degrees from the University of Twente, Enschede, The Netherlands, in 2006 and 2010 respectively, both in electrical engineering. From 2010 to 2016, he was a principal engineer and design manager with Marvell Semiconductor, Santa Clara, CA, focusing on wireless transceiver circuits. He is now an Engineering Director with Credo Semiconductor, Milpitas, CA, working on high-speed SerDes. He has published 20 papers and holds 8 patents. He is an IEEE senior member.