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01 Mar 2021
Abstract - The growing needs of efficient data transmission and storage are driving information delivery technologies to new frontiers. Either in the new radio (NR) links of 5G communications, or in emerging non-volatile memories (NVMs) with continuously increasing capacity, error correcting codes (ECCs) are essential and crucial in maintaining the data correctness. In this tutorial, we will cover major concepts in ECC design and architecture, including multi-Gb/s LDPC-BC, energy-efficient LDPC-CC, and Polar/Turbo decoders that fulfill different requirements in various 5G scenarios. For NVM applications, we will introduce 1-error and 2-error correcting scheme with parallel architectures for NOR flash, as well as BCH and LDPC coding schemes for NAND/3D-NAND, to address low-latency and high-throughput solutions.
Bio - Hsie-Chia Chang received the B.S., M.S., and Ph.D. degrees from National Chiao Tung University, Hsinchu, Taiwan, in 1995, 1997, and 2002, respectively, all in electronics engineering.
He was with OSP/DE1, MediaTek Corporation, from 2002 to 2003, where he was involved in decoding architectures for combo single chip. In 2003, he joined the faculty of the Electronics Engineering Department, National Chiao-Tung University, where he has been a Professor since 2010. His research interests include algorithms and VLSI architectures in signal processing, in particular, error control codes and crypto-systems. He has published more than 100 IEEE journal/conference papers, and more than 50 U.S./Taiwan patents. Recently, he has focussed on designing high code-rate ECC schemes for flash memory, PUF implementation for secure MCU system, and multi-Gb/s chip implementations for wireless communications. Dr. Chang served as the Deputy Director General with the Chip Implementation Center, Taiwan, since 2017. He has also served as an Associate Editor of the IEEE Transactions on Circuits and Systems I: Regular Papers since 2012, as well as served as a Technical Program Committee Member of the IEEE Asian Solid-State Circuits Conference from 2011 to 2013, and the International Solid-State Circuits Conference in 2018. He was a recipient of the Outstanding Youth Electrical Engineer Award from the Chinese Institute of Electrical Engineering in 2010, and the Outstanding Youth Researcher Award from the Taiwan IC Design Society in 2011.
Bio - Hsie-Chia Chang received the B.S., M.S., and Ph.D. degrees from National Chiao Tung University, Hsinchu, Taiwan, in 1995, 1997, and 2002, respectively, all in electronics engineering.
He was with OSP/DE1, MediaTek Corporation, from 2002 to 2003, where he was involved in decoding architectures for combo single chip. In 2003, he joined the faculty of the Electronics Engineering Department, National Chiao-Tung University, where he has been a Professor since 2010. His research interests include algorithms and VLSI architectures in signal processing, in particular, error control codes and crypto-systems. He has published more than 100 IEEE journal/conference papers, and more than 50 U.S./Taiwan patents. Recently, he has focussed on designing high code-rate ECC schemes for flash memory, PUF implementation for secure MCU system, and multi-Gb/s chip implementations for wireless communications. Dr. Chang served as the Deputy Director General with the Chip Implementation Center, Taiwan, since 2017. He has also served as an Associate Editor of the IEEE Transactions on Circuits and Systems I: Regular Papers since 2012, as well as served as a Technical Program Committee Member of the IEEE Asian Solid-State Circuits Conference from 2011 to 2013, and the International Solid-State Circuits Conference in 2018. He was a recipient of the Outstanding Youth Electrical Engineer Award from the Chinese Institute of Electrical Engineering in 2010, and the Outstanding Youth Researcher Award from the Taiwan IC Design Society in 2011.
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