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21 Jun 2019
Abstract- Design constraints and operating limits of high voltage SiC DMOSFETs are presented. Low channel mobilities in SiC force MOSFET design points for optimum performance to suffer from short-channel effects.
Static characteristics - forward I-V, threshold voltage are presented.
Switching times of less than 30 nano-seconds were recorded for 2kV
switching. An investigation of the operating limits and failure modes
for SiC DMOSFETs under unclamped inductive switching (UIS) and
short-circuit conditions is performed. Maximum single-pulse avalanche
energies (EAS) of 13.75 J/cm2 and avalanche withstand times (tAV) as
high as 71 �s are recorded. The variation of EAS and tAV with load
inductance (or avalanche current) is quantified. Stability of the key
DMOSFET performance characteristics including RDS,on, VTH, body-diode, gate/drain leakage currents and terminal capacitances under both
single-pulse and repetitive (up to 1000 shots) avalanche conditions
are presented. Short-circuit withstand times (tSC) in the range of 3-14 �s are presented on the DMOSFETs, The impact of various factors
such as the device design, gate drive voltage, DC link (drain) voltage, and operating temperature on the tSC is quantified. The evolution of the I-V and C-V characteristics under short-circuit operation is examined, and failure mechanisms are suggested.
Bio- Dr. Ranbir Singh, received a Ph.D. and MS degrees in Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, and B. Tech from Indian Institute of Technology, Delhi. He founded GeneSiC Semiconductor Inc. in 2004. Prior to that he conducted research on SiC power devices first at Cree Inc, and then at the NIST, Gaithersburg, MD. In 2012, EE Times named Dr. Singh as among "Forty Innovators building the foundations of next generation electronics industry.� In 2011, he won the R&D100 award towards his efforts in commercializing 6.5kV SiC Thyristors. He has published over 200 journal and conference papers, is an author on 28 issued US patents, and has authored a book.
Static characteristics - forward I-V, threshold voltage are presented.
Switching times of less than 30 nano-seconds were recorded for 2kV
switching. An investigation of the operating limits and failure modes
for SiC DMOSFETs under unclamped inductive switching (UIS) and
short-circuit conditions is performed. Maximum single-pulse avalanche
energies (EAS) of 13.75 J/cm2 and avalanche withstand times (tAV) as
high as 71 �s are recorded. The variation of EAS and tAV with load
inductance (or avalanche current) is quantified. Stability of the key
DMOSFET performance characteristics including RDS,on, VTH, body-diode, gate/drain leakage currents and terminal capacitances under both
single-pulse and repetitive (up to 1000 shots) avalanche conditions
are presented. Short-circuit withstand times (tSC) in the range of 3-14 �s are presented on the DMOSFETs, The impact of various factors
such as the device design, gate drive voltage, DC link (drain) voltage, and operating temperature on the tSC is quantified. The evolution of the I-V and C-V characteristics under short-circuit operation is examined, and failure mechanisms are suggested.
Bio- Dr. Ranbir Singh, received a Ph.D. and MS degrees in Electrical and Computer Engineering, North Carolina State University, Raleigh, NC, and B. Tech from Indian Institute of Technology, Delhi. He founded GeneSiC Semiconductor Inc. in 2004. Prior to that he conducted research on SiC power devices first at Cree Inc, and then at the NIST, Gaithersburg, MD. In 2012, EE Times named Dr. Singh as among "Forty Innovators building the foundations of next generation electronics industry.� In 2011, he won the R&D100 award towards his efforts in commercializing 6.5kV SiC Thyristors. He has published over 200 journal and conference papers, is an author on 28 issued US patents, and has authored a book.
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