Hardware Security and Safety of IC Chips Video
Makoto Nagata
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Members: FreeSSCS
IEEE Members: $8.00
Non-members: $15.00Length: 01:15:00
16 Apr 2021
Abstract: IC chips are key enablers of smartly networked society and need to be more compliant to security and safety. Semiconductor products for autonomous vehicles abide stringent regulations and requirements. In parallel to circuits and systems developments that designers visibly engage toward the performance and functionality of such products, the countermeasure tricks are proactively exploited against spontaneous disturbances within IC chips and even intentional attacks by an adversary.
This talk will start from Electromagnetic Compatibility (EMC) techniques of IC chips on the safety side, toward EMC aware design, analysis and implementation. Then, the challenges will be discussed about the design of IC chips for the higher level of hardware security (HWS). Crypto-based secure IC chips are investigated to avoid the risks of side-channel leakages and side-channel attacks, with the Si demonstrators that utilize analog techniques to protect digital functionality. The EMC and HWS disciplines are bridged from the electromagnetic (EM) standpoint to establish the design principles of IC chips toward security and safety.
Bio: Makoto Nagata received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, in 1991 and 1993, respectively, and a Ph.D. in electronics engineering from Hiroshima University, Hiroshima, in 2001. He was a research associate at Hiroshima University from 1994 to 2002, an associate professor at Kobe University from 2002 to 2009 and promoted to a full professor in 2009. He is currently a professor of the graduate school of science, technology and innovation, Kobe University, Kobe, Japan. He is a senior member of IEICE and IEEE.
His research interests include design techniques targeting high-performance mixed analog, RF and digital VLSI systems with particular emphasis on power/signal/substrate integrity and electromagnetic compatibility, testing and diagnosis, three-dimensional system integration, as well as their applications for hardware security and safety.
Dr. Nagata has been a member of a variety of technical program committees of international conferences such as the Symposium on VLSI Circuits (2002-2009), Custom Integrated Circuits Conference (2007-2009), Asian Solid-State Circuits Conference (2005-2009), International Solid-State Circuits Conference (2014-2017), European Solid-State Circuits Conference (2020-) and many others. He is chairing the Technology Directions subcommittee for International Solid-State Circuits Conference (2018-present). He is also serving as SSCS AdCom member (2020-). He is currently an associate editor for IEEE Transactions on VLSI Systems (2015-present). He was a technical program chair (2010-2011), a symposium chair (2012-2013) and an executive committee member (2014-2015) for the Symposium on VLSI circuits, and also a chair for IEEE SSCS Kansai Chapter (2017-2018).
This talk will start from Electromagnetic Compatibility (EMC) techniques of IC chips on the safety side, toward EMC aware design, analysis and implementation. Then, the challenges will be discussed about the design of IC chips for the higher level of hardware security (HWS). Crypto-based secure IC chips are investigated to avoid the risks of side-channel leakages and side-channel attacks, with the Si demonstrators that utilize analog techniques to protect digital functionality. The EMC and HWS disciplines are bridged from the electromagnetic (EM) standpoint to establish the design principles of IC chips toward security and safety.
Bio: Makoto Nagata received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, in 1991 and 1993, respectively, and a Ph.D. in electronics engineering from Hiroshima University, Hiroshima, in 2001. He was a research associate at Hiroshima University from 1994 to 2002, an associate professor at Kobe University from 2002 to 2009 and promoted to a full professor in 2009. He is currently a professor of the graduate school of science, technology and innovation, Kobe University, Kobe, Japan. He is a senior member of IEICE and IEEE.
His research interests include design techniques targeting high-performance mixed analog, RF and digital VLSI systems with particular emphasis on power/signal/substrate integrity and electromagnetic compatibility, testing and diagnosis, three-dimensional system integration, as well as their applications for hardware security and safety.
Dr. Nagata has been a member of a variety of technical program committees of international conferences such as the Symposium on VLSI Circuits (2002-2009), Custom Integrated Circuits Conference (2007-2009), Asian Solid-State Circuits Conference (2005-2009), International Solid-State Circuits Conference (2014-2017), European Solid-State Circuits Conference (2020-) and many others. He is chairing the Technology Directions subcommittee for International Solid-State Circuits Conference (2018-present). He is also serving as SSCS AdCom member (2020-). He is currently an associate editor for IEEE Transactions on VLSI Systems (2015-present). He was a technical program chair (2010-2011), a symposium chair (2012-2013) and an executive committee member (2014-2015) for the Symposium on VLSI circuits, and also a chair for IEEE SSCS Kansai Chapter (2017-2018).
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