Addressing Supply Noise in Digital Domains through Adaptive Clocking: Past, Present, and Future Video

Abstract: Energy efficiency remains a key concern in modern SoCs. Despite tremendous advances in packaging and power delivery, the margins required to withstand supply voltage noise still play a dominant role in dictating SoC energy efficiency. Starting from early efforts that injected charge into the supply, the field has evolved toward instruction throttling and adaptive clocking which are now widely used. Even so, there remains significant room for further margin reduction.In this talk, we briefly introduce the problem of supply noise and examine several adaptive clocking techniques that have been adopted over the years to address this challenge. We examine their existing limitations to motivate the design of several recent adaptive clocking innovations that unify voltage regulation and clock generation into a single entity. We will more closely examine the Unified Clock and Power (UniCaP) architecture as an example of such an approach. The effectiveness of this technology and its enabling capabilities will be discussed through multiple test-chip demonstrations and measurements, including a performance-regulated 65nm Cortex M0 processor which achieves 98% voltage margin Finally, we discuss some limitations of UniCaP that inform both its existing usability and future directions.


Bio: Visvesh S. Sathe received the B.Tech. degree from the Indian Institute of Technology, Bombay and the M.S. and Ph.D. degrees from the University of Michigan, Ann Arbor. He is currently an Associate Professor of Electrical and Computer Engineering at the University of Washington where he leads the Processing Systems Lab (PSyLab), focused on research associated with energy-efficient computing and implantable electronics. Prior to joining the University of Washington, he served as a Member of Technical Staff in the Low-Power Advanced Development Group at AMD, where his research focused on inventing and implementing circuit, clocking and supply mitigation technologies in next-generation microprocessors. These technologies include high-speed digital circuits, adaptive clocking for supply noise mitigation and resonant clocking. His current research interests include implementation of run-time hardware control and optimization in digital and mixed-signal systems over a range of applications. He is the recipient of an NSF Career award in 2019 and more recently, the Intel outstanding researcher award in 2021. He serves on the technical program committee of the IEEE Custom Integrated Circuits Conference, and as a distinguished lecturer of the Solid-State Circuits Society.