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3D Integration of Vertical Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers
15 Dec 2020

3D Integration of Vertical Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers

  • EDS
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    Non-members: $20.00
Wafer Scale Integration of Double Gated WS2 Transistors in 300 mm Si CMOS Fab
15 Dec 2020

Wafer Scale Integration of Double Gated WS2 Transistors in 300 mm Si CMOS Fab

  • EDS
    Members: $5.00
    IEEE Members: $10.00
    Non-members: $20.00